Can verilog file (.v) used as library??

Hi ,

Can anyone tell me if a verilog file can be used as a library file??

Below given module is a library?? or it is a normal verilog file??
`celldefine
module(..)
.....
endmoduel
`endcelldefine

regards,
Tauqueer

Which tool are you using? For Synopsys Design Compiler I don't think it supports it.
Try checking out the read_lib command and the -format option to see what it can do.

yes, you can use it as lib!

I am using magma blast.

Please tell me how the tool will treat these two library file one .v and other is .lib ??
Is there any difference in the netlist generated by synthesis tools??

Hi alam,
From the foundry, the standard cell libraries u can get are:
lef lib
timing lib
gds lib
verilog lib
noise libraries,
etc.,

The verilog file from the foundry contains the verilog code (the instantiation and the path delays).
In this all the components are independent and they are interconnected. It is a library of verilog components is an easier way to say.
The verilog file obtained from synthesis contains the gate level netlist.
That is the behavioral code given as input is replaced with the gates from the timing library you have given as input for the synthesisbased the constraints given.
Please go through the synthesis tool (for example Design Compiler or RTL Compiler) manuals.
It might help you.
Now the question is can u use a verilog file as library?
Of course you can but for simulation only.
Thanks.