milosavljevic
Newbie level 4
Dear all,
I would like to ask you about the problem that i have in simulink for shift registers. In the attachment i am sending a simulink file with a single d flip flop. Basically the problem that i have is at the Q output of the flip flop.
If i have 10 clock cycles and the sampling time is 1 of the signal generator, theoretically i will then shift 10 bits at the output of the flip flop after 10 seconds. However, due to the clock (i belive) for a single bit at the Q output flip flop produces 2 bits, e.g. instead of logic 1 it gives 11 (this can be observed by sending the output as an array to the workspace). Therefore, if the input sequence is 110101 for instance the output will be 11 11 00 11 00 11. This creates the problem when i wnat to convert the output of the shift registers to integer using bit-to-integer converter.
How can i avoid this problem? Eventually i am trying to do serial to parallel converter.
Any comments on this metter will be very much appreciated.
Thank You.
Regards.
Milos
I would like to ask you about the problem that i have in simulink for shift registers. In the attachment i am sending a simulink file with a single d flip flop. Basically the problem that i have is at the Q output of the flip flop.
If i have 10 clock cycles and the sampling time is 1 of the signal generator, theoretically i will then shift 10 bits at the output of the flip flop after 10 seconds. However, due to the clock (i belive) for a single bit at the Q output flip flop produces 2 bits, e.g. instead of logic 1 it gives 11 (this can be observed by sending the output as an array to the workspace). Therefore, if the input sequence is 110101 for instance the output will be 11 11 00 11 00 11. This creates the problem when i wnat to convert the output of the shift registers to integer using bit-to-integer converter.
How can i avoid this problem? Eventually i am trying to do serial to parallel converter.
Any comments on this metter will be very much appreciated.
Thank You.
Regards.
Milos