can someone please explain the concept of weak 0 and weak 1?

[ms_90]

i know that PMOS is used for getting strong 1 and NMOS for getting strong 0. Also, if w will use NMOS as pull up it will only b able to pull the output upto vdd-vt and in case of PMOS in pull down it will be vss+vt. so can someone please explain this voltage changes at device level with respect to the working of MOSFET or please suggest any suitable links or documents to read.


thanks in advance

 

[yadavvlsi]

This results in less output voltage swing and less noise margins.
https://www.evlsi.com/viewtopic.php?f=11&t=6

 

[ms_90]

thanks yadavvlsi...
i already know it...but i want to know exactly that how the voltage will be vdd-vt and vss+vt ?
can you please explain it?

 

[yadavvlsi]

Please check below link:
https://www.vlsiinterviewquestions.org/2012/02/22/strong-0s-and-weak-1s/

 

[ms_90]

thanks...now i got it...