Can see hierarchy after synthesizing Verilog in ISE 6.1

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Bartart

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ise 6.1 and verilog

Hi friends!!

I have a problem using Xilinx ISE and verilog files, after a synthese I am unable to see a hierarhy in floorplaner. I have check and uncheck the "keep hierarhy" in synthese options menu but still no changes.

Strange is that i don't have any kind of problem if i use vhdl code.


any idea?


thanks bart
 

ise 6.1 and verilog

this seems to be very unusual

ashish
 

Re: ise 6.1 and verilog

Hi!

The problem was solved fortunatly. Error - wrong switch in my script was the main problem. :?


bart
 

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