Can not generate Verilog using FIFO Generator in IP catalog

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slutarius

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I opened a project and tried to make a general FIFO using "FIFO generator". Target language is set to Verilog. When it is done, but I received a VHDL type of source code instead of Verilog.
In same project, I took a Clock Wizard and can get Verilog type of an MCMM.

Does anyone meet the same issue ? Is that the exception for FIFO generator ?

I was trying to google it before hands, but no suitable info.
 

Some of the IP Xilinx produces only come in either VHDL or Verilog. I think it has more to do with which group (location) that implements the IP.
 
Thanks for your all comment. I will contact tool vendor.
It is available on Spartan6, but not on Kintex7 series though.
 

slutarius said:
Thanks for your all comment. I will contact tool vendor.
It is available on Spartan6, but not on Kintex7 series though.
Click to expand...

I predict the answer will be...

"Sorry, we don't have it in Verilog use the VHDL version Xilinx tools support mixed language designs"
 

ads-ee said:
I predict the answer will be...

"Sorry, we don't have it in Verilog use the VHDL version Xilinx tools support mixed language designs"
Click to expand...

I guess so. Moving up with a FIFO myself since it is not much on logic, but I expect something from STA and implementation. Thanks !
 

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