slutarius
Full Member level 5
I opened a project and tried to make a general FIFO using "FIFO generator". Target language is set to Verilog. When it is done, but I received a VHDL type of source code instead of Verilog.
In same project, I took a Clock Wizard and can get Verilog type of an MCMM.
Does anyone meet the same issue ? Is that the exception for FIFO generator ?
I was trying to google it before hands, but no suitable info.
In same project, I took a Clock Wizard and can get Verilog type of an MCMM.
Does anyone meet the same issue ? Is that the exception for FIFO generator ?
I was trying to google it before hands, but no suitable info.