You can use any device you want as the "victim" - that's the
point of making a testbench really.
But you have to expect the MOSFET model may be a fair bit
short of reality when you get to the margins, such as the
accuracy of breakdown I-V (often entirely absent from IC
FET models, possibly emulated in power FET macromodels).
And you can safely bet there is nothing at all for modeling
the weak / hot spots and destructive phenomena, which
are pretty much the whole point of ESD testing.
So your simulation results, at best, will show the response
of the undamaged FET, and you need to -criticize- these
results against some real world data - such as the TLP
peak voltage that is shown to not cause damage, and
if your simulated voltage exceeds this then you need a
better protection, etc.