Re: Can i use Matlab(Simulink)as data source to FPGAVirtexII
boardlanguage said:
salma ali bakr said:
You need to use System Generator
Feel free to ask me about it, I'm working with it these days...
Regards,
Salma
So is system-generator just a co-simulation linker between Simulink and an HDL-simulator? Or does it do more (like help you write synthesizeable VHDL/Verilog code?)
Sorry, I'm just a little confused between AccelDSP and System Generator -- it sounds ike they have some overlap.
with system generator you can create block level design...which can be converted to HDL netlist or bitstream...
the block level simulations can be done in wavescope, which is an integrated simulator...
for the functional simulation of the generated HDL code, you can just use modelsim for instance! (take into account that the generated HDL code is some sort of spaghetti code, since it employs cores from core generator!!)
you can then take this code to ISE and do the synthesis, place and route, etc etc till generating the bitfile to be downloaded on the FPGA...or else, just generate the bitfile from system generator itself by choosing the bitstream option..\
in system generator you can do hardware co-simulation also, which means that you simulate the design in software (the simulink environment of matlab) or simulate it on the actual hardware...so you use it to compare the results and know whether the hardware is functionally correct or not....and you can use it for reducing simulation time by doing the hardware simulation only and observing the results...
regarding acceldsp, it's integrated with system generator...and helps in synthesizing the algorithmic level design in matlab to RTL ...and generates an IP block, which is then added to a system generator model to make a complete system which can be simulated, used to generate netlist or bitfile, etc etc...so acceldsp can't be standalone, it's always integrated with system generator and only provides this extra [matlab to RTL] part which wasn't available before!!