Can I solve the phase ambiguity of half rate Bang-Bang phase detector based CDR?

[ruwan2]

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**broken link removed**

Hi,
I simulate a half rate Bang-Bang phase detector based CDR, which has 4 phases output: 0, 45, 90 and 135. The VCO output 0 and 90 outputs are used to sample data signal. I find that the VCO can converge to (lock) to the data with two (180 opposite phases) under two conditions. The two cases has two different phase errors while the frequencies are the same.

I do not find error yet. Should the phase ambiguity exist? Or, what is wrong in my design/simulation?



Thanks,


I know that it is right now.

 

[biff44]

only a ham would consider a "bang bang" pll. How about just getting a modern PLL chip and using it properly?