Thanks, Bigboss!
Since W/L ratio increases ( not exaggerated ), the matching also increases.
Does it means W/L or W*L? Because if it is W/L, I can make small L and large W, which can have a good matching. If it's W*L, I can also make large L to increase matching. Someone told me that I can make large L to increase matching. It makes me puzzled.
Simulation models are less accurate for small sized semiconductor components.
I don't mean small size. I mean if L>W(both are not the minimum size), is simulation models are less accurate?
By the way, If L and W is too large, for example 0.35um technology, L=3um, W= is 50u, will the simulation models be less accurate?
It need much practical experience which I really lack of. Thanks!
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Thanks,dick_freebird. May I ask where I can find PDK. Now I have many docs from foundry such as Design rules, layout rules manual, electrical parametes,ESD and latch-up guidlines. But I don't know which one is PDK?
And if I search in PDK, what's key word I should choose?
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It's been the norm for a long time in larger-feature analog
MOS design. Whether the model covers the geometry is
dependent on what the foundry thinks it needs to support.
For mixed signal, almost certainly the L>W case will be
covered (and PDK docs should tell you the limits of accurate
geometry modeling explicitly). For "plain digital" you may not
see much emphasis, and maybe sloppy modeling, for long
devices as these would have no use in core logic or high
speed I/Os (or, would be considered "non-critical").
Thanks,dick_freebird. May I ask where I can find PDK. Now I have many docs from foundry such as Design rules, layout rules manual, electrical parametes,ESD and latch-up guidlines. But I don't know which one is PDK?
And if I search in PDK, what's key word I should choose?