Can I do this in VHDL?

[barry]

Maybe I'm trying to do something I can't, but it seems like I should be able to.

Here's a snippet:

signal big:std_logic_vector(15 downto 0);
signal little:std_logic_vector(3 downto 0);
.
.
.
little<=(big-x"0010")(3 downto 0);

This is part of a testbench I'm using in Active-HDL, and it doesn't like the assignment. The error I get says it wants a ";" before the "(3 downto 0)". If I eliminate the "(3 downto 0)", it compiles ok, but then fails at runtime (as would be expected).

Any thoughts, guys?

 

[TrickyDicky]

Hmm, I always thought you could, but apparently not.

However, you can slice a function return, rather than an operator

---

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
entity test is
end entity test;
 
architecture rtl of test is
  signal a : signed(15 downto 0);
  signal b : signed(3 downto 0);
  
  function minus(a : signed) return signed is
  begin
      return a - 1;
  end function;
  
begin
 
  b <= minus(a)(3 downto 0);
 
end rtl;

---

 

[barry]

Thanks Tricky

Just thought it would be nice if it worked MY way.

This might actually be a problem with the active-HDL compiler. Since it's a testbench, I haven't tried to synthesize it. I might just do a test to see if it synthesizes.

 

[TrickyDicky]

It failed in modelsim for me, so I assume its a language thing.

 

[barry]

Well, that does it. I'm making my own HDL.

 

[TrickyDicky]

Haha
First try AHDL then get really mad...