can I can include 2 statement inside if condition in Verilog

[Irfansw07]

VerilogA in Analog

Can anyone help me out in giving answer if I can include 2 statement inside if condition in VerilogA....

I mean to say when I write like this
if ( a = 0 and b = 0) begin

then Above statement is incorrect in VerilogA and showing error
Can some one please tell me how to write in correct form

Thanks in advance

 

[Loktik_Vitalij]

VerilogA in Analog

maybe if ( a == 0 and b == 0)
or
if (( a == 0) && (b == 0))