fenfei
Member level 1
Hello everyone:
Recently,I have tried to make a frac-N PLL for 1G~2G. I used the ADF4156 and ADF4157,which's datasheet says that the fractional spur could be removed by delta-sigma and dither.
But in my circuits,both chips all have strong fractional spurs. that means if the FRAC register is set to 0, all work very well, low phase noise, no spurs. But if the FRAC is not 0 ,the spurs appear.
In ADF4156 ,the spur appears at 1/MOD*fPFD offset. In ADF4157 ,the spur appears at FRAC/MOD*fPFD offset.
I have tried to change the loop filter,PFD freq,output freq,etc. Nothing works.
I begin to doubt if the chip really could remove frac spurs.
Anyone have used the simillar fractional N PLL?
could anyone give me some suggestion?
my PLL spec are: fPFD 30MHz,loop width 50kHz ,phase margin 45,freq step 10kHz
Recently,I have tried to make a frac-N PLL for 1G~2G. I used the ADF4156 and ADF4157,which's datasheet says that the fractional spur could be removed by delta-sigma and dither.
But in my circuits,both chips all have strong fractional spurs. that means if the FRAC register is set to 0, all work very well, low phase noise, no spurs. But if the FRAC is not 0 ,the spurs appear.
In ADF4156 ,the spur appears at 1/MOD*fPFD offset. In ADF4157 ,the spur appears at FRAC/MOD*fPFD offset.
I have tried to change the loop filter,PFD freq,output freq,etc. Nothing works.
I begin to doubt if the chip really could remove frac spurs.
Anyone have used the simillar fractional N PLL?
could anyone give me some suggestion?
my PLL spec are: fPFD 30MHz,loop width 50kHz ,phase margin 45,freq step 10kHz