256x256x25x16=26214400
and ~26 MHz is very easy in an FPGA even a Spartan 6, which can easily handle designs running at 200MHz. So running the entire design at the output pixel clock rate is probably the simplest way to implement this design. Just use clock enables in your code to operate some portions of the design at the lower clock rates. You probably won't even need to add multicycle constraints as 26 MHz should still be easy to meet timing with.