can cadence ic5141 utilize the stand cell library to layout?

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swgchlry

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I'm designing some very small digital circuits, <100 gates. Could ic5141 read the tsmc stand cell library to extract the cells and instantiate these cells in layout editor? If can't, is there a simple way to get the layout without employee Synopsys DC and Canence P&R Tools?
 

basically you can instantiate the layout cell into your layout. However, your layout library should provide a full layout view (all GDS layers) in order to get all extracted devices.

If the library only provide the blackbox view, you again extract the spice from the layout, but you can get the subcircuit level netlist.

hope this is helpful.

mm
 

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    swgchlry

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