Thank you for your comments goldsmith.Hi why you didn't use mosfets ? what the .... are those that you used ? why you used sine wave and then .... ? it is pretty simple use four vpulse simply !
Best Wishes
Goldsmith
There is no designated operation frequency and o/p voltage, duty cycle 0.5. According to my supervisor, this test is simply to make V1 in phase with the output Vc1 while according to his idea of the operation of vccs and h bridge they should be.What should be the operation frequency and duty cycle and out put voltage ? . if you tell them to me , i can simulate it and show you the result .
Best Wishes
Goldsmith
zqbeijing,
You must provide proper delay in order to avoid simultaneous conduction of switches at same side of H-bridge.
Regarding use of switches instead transistors (BJT, MOSFET,IGBT,etc...), makes sense, once the first task is to perform simulation correctly, and then insert real-world devices.
+++
Hi FvM:Where's the bus voltage source? The waveforms suggests that the node is floating.
So I think that is one reason why my supervisor asked me to use ideal switches first because there are some non ideal characteristics by using fets.Hi again
Afternoon i'll send it .
And a notation regarding things that andre said : i think he is referring to the dead time to prevent overlapping . as you know each mosfet has dealy time and GS capacitor effect , thus it is pretty bad if you don't create dead time ! because at a little time VDC will connect to the ground .
Best Wishes
Goldsmith
I agree, that the "10V" node name suggests a DC supply. It would be easy to show the VDC source in the schematic to clear the doubts.Supply voltage is 10V as shown on the schematic.
It should be alright to perform a simulation.
Thanks
No doubt about. But it should work with ideal switches as well. I'm often using switch models for a functional simulation of complex power electronics circuits, e.g. when focussing on the controller design.But if you want to build this circuit in practice all things will change !
I agree, that the "10V" node name suggests a DC supply. It would be easy to show the VDC source in the schematic to clear the doubts.
Anyway. You surely agree, that the S1 and S2 switch voltages should sum to 10 V. Please help may to identify this summation in your waveform, see the below detail. In my understanding the waveforms shows |Vbus| < 1 V.
No doubt about. But it should work with ideal switches as well. I'm often using switch models for a functional simulation of complex power electronics circuits, e.g. when focussing on the controller design.
Hi again
I came back ! see below please :
View attachment 75708
View attachment 75709
But if you want to build this circuit in practice all things will change !
Best Wishes
Goldsmith
What ? are you referring to the voltage across the gate of M1 ? of course it is in phase with vpulse 1 because those are in parallel together . perhaps you're referring to another thing ?o you think the voltage difference across the output of G1 can be in phase with V1?
No, i was referring to the voltage across the output ends of voltage controled current source G1 in my shcmatic...now the problem about how the switches can be controled has been solved, i feel confused with the characteristics of that vccs...What ? are you referring to the voltage across the gate of M1 ? of course it is in phase with vpulse 1 because those are in parallel together . perhaps you're referring to another thing ?
The polarity of the current source is indicated by an arrow and is according to usual SPICE rules, current flowing from + to - node. In case of doubt, you can refer to the PSPICE user manual.
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