kawaiicat
Member level 1
i want to do mix signal design, for the analog signal, i have spice simulator
so if i want to make the digital part( i dont' want to use spice as it is not very efficient , sim transient take me long time)
i want to write verilog to verify it. or i got circuit in my mind, i want to translate my circuit (probably hspice netlist) to verilog code to verify it?and if i do it in verilog code, can i output a hspice netlist?...what i can use and if i want to do autoplace and route..what i can use..hopefully i want a GDS file for the final output..
i am looking some software, see any trial version or in reasonable price, in PC platform..anyone can help..probably i can't afford synopsys, cadence..metorgraphic...
really urgent..please letme know, in linux or unix platform will be my 2nd choice
thanks thanks thanks alot
so if i want to make the digital part( i dont' want to use spice as it is not very efficient , sim transient take me long time)
i want to write verilog to verify it. or i got circuit in my mind, i want to translate my circuit (probably hspice netlist) to verilog code to verify it?and if i do it in verilog code, can i output a hspice netlist?...what i can use and if i want to do autoplace and route..what i can use..hopefully i want a GDS file for the final output..
i am looking some software, see any trial version or in reasonable price, in PC platform..anyone can help..probably i can't afford synopsys, cadence..metorgraphic...
really urgent..please letme know, in linux or unix platform will be my 2nd choice
thanks thanks thanks alot