rhythamic_guy
Newbie level 1
Hai everybody,
My name is Raj, I am working on sigma-delta ADC. I am trying to simulate the 1st order sigma-delta ADC in cadence. In ahdlib there is a 1st order sigma-delta ADC, it is in veriloga code.
can anybody help me regarding what values to be given to a parameter to get a output. And can anybody help me what the parmaters do the job, such as Vth, Vhigh, Vtran_clk etc..,
can anybody tell me clearly about the parameters.
I hope someone can help me
Thanks in advance
Regards,
raj
My name is Raj, I am working on sigma-delta ADC. I am trying to simulate the 1st order sigma-delta ADC in cadence. In ahdlib there is a 1st order sigma-delta ADC, it is in veriloga code.
can anybody help me regarding what values to be given to a parameter to get a output. And can anybody help me what the parmaters do the job, such as Vth, Vhigh, Vtran_clk etc..,
can anybody tell me clearly about the parameters.
I hope someone can help me
Thanks in advance
Regards,
raj