Calculation the capacitance of a mosfet c(VGS)

[harry456]

Calaculation the capacitence of an mosfet c(VGS)

I tried to calculate the capacitance of simulated MOSFET (a la C = I / dV/dt) with an connected drain/source contact but why is there a different between the gate current and the current at the current-source? Is the current-source drawing a current from the bulk?

 

[KlausST]

Re: Calaculation the capacitence of an mosfet c(VGS)

Hi,

Your measurement isn't clear to me...

But measuring with drain and source connected isn't very informative for switching speed.
Because of the miller effect you need to differentiate..

Klaus

 

[harry456]

Re: Calaculation the capacitence of an mosfet c(VGS)

My objective is to see how the transistor behaves as an (gate-)capacitor and in the literature there are a lot of depictions that show the different modes of the fet a la accumulation, depletion and inversion. Therefore I tried to calculate the capacitence of the fet.

My question is, why is the current that flows into the fet's gate not the same as the current that flows through the voltage-source? Does the voltage-source draw current through the bulk?

 

[KlausST]

Re: Calaculation the capacitence of an mosfet c(VGS)

Hi,

to be true i can´t find the relation between schematic and graphs. I tried names and color, but didn´t find it... Also, what is current, and what is voltage.

To measure the current you need a signal where the voltage range is the regiion where the FET is well within the "open" state.

A very save method for capacitance measurement is to use a sine voltage signal and correlate the current with the voltage. For capacitance calculation only take the imaginary part of the current.
The real part of the currrent is caused by ohmic resistance (bad isolation, DC resistance, FET conductivity)
But mabe it´s not worth the effort.

Klaus

 

[dick_freebird]

Re: Calaculation the capacitence of an mosfet c(VGS)

You should drill down into the model hierarchy and see
whether it includes capacitances besides the core FET
(e.g. some metallization RLC in a macro-layer / subckt).
This is becoming more common especially for RF destined
technologies (and what, anymore, isn't?).

A small rectangular (or nearly so) current impulse, and
measurement of the voltage step, is a very easy method.
You know Q, you read V, C falls out of the equation
(dQ=CdV). Provided that your Q is small-signal-scale
this is probably realistic enough.