Calculation of static power in sram

[swethabysani]

Can any one tell me whether power calculated in standby mode is static power or not?
If not how to calculate static power in cadence or hspice?

 

[FvM]

whether power calculated in standby mode is static power or not

Yes, standby (no signal transitions) sounds reasonable.

 

[dick_freebird]

It is not necessarily true that disabled static power equals
enabled, static-input power. Clever designers might have
added power-strobing features to the sense, write ckty
and so on, especially if the enable-Q prop delay has a lot
more slack than the A-Q delay. Presuming there is a chip-
wide enable (e.g. CS) present along with OE, WE.

I'd recommend you check both, and have a look at some
modern competitor (or source of the part in question, if
this is about some actual product IC) datasheets to see
whether they spec these two cases separately, or assert
a specific test condition which you should then follow.

 

[FvM]

The considerations are generally true, but the OP is apparently asking about elementary 6T SRAM cells (homework problem).