DimaKilani
Member level 1
Dear all,
I have designed a minimum inverter size in 65nm CMOS (W/L=150nm/60nm). I want to calculate the current consumption and leakage of the inverter.
I have two cases as below:
Case#1 (calculating total current): the input of the inverter is a normal clock (from 0V to Vdd). I measure the current from the supply. I_total=4.4pA
Case#2 (calculating the leakage): when Vin=0, PMOS is on and NMOS is off so it is leaking and I_leak_nmos= 5.33pA. On the other hand when Vin=Vdd, PMOS is off and NMOS is on so that PMOS is leaking and I_leak_pmos=3.35pA
Now the problem here is that the I_total < I_leak_nmos + I_leak_pmos. I know it is not logical since I_total= I_leak_pmos + I_leak_nmos + I_transition
In addition, I noticed that I_total= (I_leak_pmos + I_leak_nmos)/2. Is there something wrong?!
Please help. Thanks in advance.
I have designed a minimum inverter size in 65nm CMOS (W/L=150nm/60nm). I want to calculate the current consumption and leakage of the inverter.
I have two cases as below:
Case#1 (calculating total current): the input of the inverter is a normal clock (from 0V to Vdd). I measure the current from the supply. I_total=4.4pA
Case#2 (calculating the leakage): when Vin=0, PMOS is on and NMOS is off so it is leaking and I_leak_nmos= 5.33pA. On the other hand when Vin=Vdd, PMOS is off and NMOS is on so that PMOS is leaking and I_leak_pmos=3.35pA
Now the problem here is that the I_total < I_leak_nmos + I_leak_pmos. I know it is not logical since I_total= I_leak_pmos + I_leak_nmos + I_transition
In addition, I noticed that I_total= (I_leak_pmos + I_leak_nmos)/2. Is there something wrong?!
Please help. Thanks in advance.