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calculating log and exponentials in verilog

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May 25, 2004
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log of exponentials

i have heard that a divide by 2 circuit takes alot of space in FPGA so it is usually implemented with a shifter.

now the problem is that i have to calculate both logs and exponentials and i think it wont be much efficient in terms of silicon area. does any one know how to do this?

if log and exp are 2 based, i think it can be implemented with shifter too
but for log, it needs multiple cycles, similar with classical divider


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If your application can tolerate numerical roundoff, simply put your math tables into ROMs. The FPGA's built-in RAMs are a good way to implement small ROMs.

If you can't do that, the next question is how fast does the calculation need to be, and how much numerical precision?


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actually im trying to implement turbo codes on a Spartan 3 FPGA. the calculations should be precise and fast.

the encoder side is easy and it can be modeled by an FSM. but the problem is the decoder side. for the decoding part i have to take the log of the sums of exponentials (i know it sounds crazy) and this has to be done again and again.

i thought of doing this with microblaze core but i havent worked on microblaze and i havent worked on XPS. then i thought of using xilinx sysgen but nobody around me has used it (or seen it) before and the evaluation version available for download is very big.

and there is one other concern, i have an XC3S200. but i just went to altium's site and their livedesign evaluation kit now comes with an XC3S1000. so i can go up to XC3S1000 but i cant afford any dev board above that.

plz guys help me out

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