These tight tolerances are given in order to minimize the skew within the group. +/-25mils is equivalent to ~10ps timing skew.
There is a max. length to the first dimm and another max. length between the dimm's them self. you also need to consider load and termination.
The official spec's for DDR2 are JEDS79-2E from Jedec.
I don't understand what value do you want to calculate.
I just don't have the concept of calculating the skew budget for DDR2 board trace.
Instead of considering flight time, it seems like we need to take into consideration of setup and hold time according to Intel's note.
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Thanks Buenos for your excel file, it's an amazing work indeed!