Cadence TSMC 0.35um, Differential amp design issue with MOS in Triode

[gangnam_style]

Hello,
I've working on a differential amp with current mirror loads.
The issue I'm facing is, I'm not able to get the load (PMOS) to saturation region. Tried varying the W/L and still the PMOS remains in Triode.
I've seen another 'not-so' normal thing w.r.t to the PMOS loads, when I do the DC operating point analysis using the Analog Design Environment, I see that Vgs>Vth, as well as Vds>Vgs-Vth, however the region is "1" (triode). Can anyone explain the reason behind this?(Vds=-54.24m , Vgs= 797.3m Vth=-746.7m)

Also, please suggest the efficient way to drive all the FET's into saturation.(W/L ratios)

I do not have any high gain requirement, I need around 40dB gain, with ICMR of 2V. I am using a current reference of 10uA.
I'm giving a differential input with 1.5V DC, and 1mV AC. (Correct me, if I need to vary this one as well)
Please see the attached picture for the schematic view.

 

[gangnam_style]

I resolved this issue by modifying the circuit, as shown here
I need a gain of 40dB. However, my current gain is around 34dB.

Kindly suggest ideas to increase the gain, I tried reducing the current, by varying the W/L ratios, and reducing the input DC doesn't seem to increase the gain too much.
Any ideas?

Thanks

 

[RIRTVLSI]

Hello sir
I have working on an op-amp ckt. but i haven't TSMC 0.35um file for simmulation ... so pls send me tsmc 0.35 um file.
e-mail:- amitvlsi09@gmail.com