Hi
I want to use cadence SoC Encounter in linux centos6
I need a tutorial how to use it.
The command how to run it
I run the cadence encounter. It is good;
Can you help me how prepare the data to import design in Encounter
How to prepare Gate level netlist (verilog)
SDC constraint and IO constraint?
For importing the different data for the design in SoC Encounter? need I instaling Synopsys design compiler ?
Yes, feed your RTL design to Cadence RC with the options and if synth passes, you'll get the netlist.I want to using RTL compiler from cadence to obtain gate level netlist from verilog code.
You team should already have one. Find it (ask your colleagues), modify it suitably and re-use it.I need the file synthesis.tcl ,I dont find it ; Should I build it?
I am the first who will work on the cadence tool,
I have no colleagues who can help me.
set_attribute lib_search_path my problem how I can choose the path of library ?
set_attribute hdl_search_path .
set_attribute library the target library?
read_hdl -v2001 Counter.v
elaborate Counter
set clock [define_clock -period 5000.0 -name clock clock]
external_delay -input {2500 2500 2500 2500} -clock clock rstn
external_delay -input {2500 2500 2500 2500} -clock clock updown
external_delay -output {2500 2500 2500 2500} -clock clock count[*]
synthesize -to_mapped
report area > area.rpt
report timing > timing.rpt
write_hdl -v2001 Counter > Counter.vh
I am using the rtl compiler to synthesize a verilog code
the script of rtl compiler
set_attribute lib_search_path my problem how I can choose the path of library ?
set_attribute hdl_search_path .
set_attribute library the target library?
read_hdl -v2001 Counter.v
elaborate Counter
set clock [define_clock -period 5000.0 -name clock clock]
external_delay -input {2500 2500 2500 2500} -clock clock rstn
external_delay -input {2500 2500 2500 2500} -clock clock updown
external_delay -output {2500 2500 2500 2500} -clock clock count[*]
synthesize -to_mapped
report area > area.rpt
report timing > timing.rpt
write_hdl -v2001 Counter > Counter.vh
I say that synthesis is a process from a software code lke verilog/Vhdl code to gate level netlist
The input are behaviroal RTL/description ,technology library,design environements,design constraints
The output optimised gate level netlist
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