Dudes,
Hope this is also a method
1) Planning and specification- likr project planning, test bech spec, verification plan
2)Design coding- Using HDL's
3)Test bench and Test cases creation-functionality Check
4)Verification
5)Synthesis- Cadence SoC enconuter,PTA,Astro any one
6)STA
7)Syntheis netlist verification
8)DFT - BIST in case of Memory design- MBIST.LBIST
9)Boundary Scan-Synopsys tool
10)Floor Planning-Cadnece Soc Encounter
11)partitoning-cadence SoC encounter
12)PnR- Cadence Nanoroute
13)Extraction Of parastic
14)Timing verification
15)Sign-off
Also differnent vendors follow diffrent steps. Cadence follow a way
magma follow another. If all tools are avaliable then i deoends on backend ppl how quick they realse GDSII netlist
Phutnae