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Cadence RTL-to-GDSII reference flow????

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s3034585

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soc encounter rtl to gds

Hi Guys
Can any one tell me wht is the reference flow for Cadence RTL-to-GDSII.
What sort of tools are used at the various stages... can any one pls tell me about it...

thanks
tama
 

raju3295

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soc encounter rtl to gds

hi
the tools will depends on ur organisation,,one can use diff tools for each step...i use only SOC First encounter for total flow .now adays Encounter timing system for signoff where iwas using same First encounter previously
 

s3034585

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ets sign-off sta

Hi Raju...
can u explain me the flow which u used... a little bit more...
i know cadence have soc encounter which can be used for the complete flow...

can u pls explain the steps and files required for it...

thanks
tama
 

omara007

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various steps in rtl to gdsii flow

you need to start with NC simulator first then when your code is functionally verified, you can start with SoC Encounter .. try the documentation of SoC Encounter .. it includes the whole flow of the platform.
 

pratap_v

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pnr flow

hi
the flow includes:
Design Import-zero RC-floorplan-placement-trail route-rc extraction-delay calculation-timing analysis-optimisation-clocktree synthesis-sta-optimisation-detail routing-signal integrity(xtalk and power analysis)-gds
 

satyakumar

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soc pnr cadence synopsys

Hi all,
Is it possible to use RTL in SOC encounter instead synthesized netlist, when I did with RTL it gave error. Can any body tell the flow how it can be used.

Thanks all
 

s3034585

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hi guys
thanks for ur replies...

can u pls state the files required for each stage. wht tool is used for rtl development it can be done in this only or then we need tools like modelsim or say nc sim for simulations and then we continue with the flow wht u have mentioned...

thnks
tama
 

omara007

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satyakumar said:
Hi all,
Is it possible to use RTL in SOC encounter instead synthesized netlist, when I did with RTL it gave error. Can any body tell the flow how it can be used.

Thanks all

SoC Encounter already contains an embedded synthesis tool called RTL compiler which accepts RTL and synthesized it to gate level netlist. For that you can, for sure, use RTL as an input to the SoC Encounter.
 

crazy_man

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RTL Synthesis - RTL Compiler
Equivalence - Conformal LEC
Floorplanning - SOC Encounter (GPS)
Placement - SOC Encounter (GPS)
CTS - SOC Encounter (GPS)
Routing - SOC Encounter (Nanoroute)
Timing Optimisation - SOC Encounter (GPS)
STA - CTE
Layout Merging - Virtuoso ICFB
Physical Verification - I dont know of any Cadence tool that does signoff DRC/LVS
 

gliss

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crazy_man said:
Physical Verification - I dont know of any Cadence tool that does signoff DRC/LVS
Assura is the sign-off DRC/LVS tool from Cadence.
 

raju3295

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generally what ever flow we follow can be simply i gave here
SYNTHESIS-florrplan-PLACEMENT-cts-optimization-mvt opt-route -si analysis-signoff
 

omara007

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raju3295 said:
generally what ever flow we follow can be simply i gave here
SYNTHESIS-florrplan-PLACEMENT-cts-optimization-mvt opt-route -si analysis-signoff

you forgot 2 important actions .. STA and Formal Verification .. both should be with u since synthesis till tape out
 

zinger

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For STA, Cadence has a stand alone tool - ETS (Encounter Timing System) provide sign-off quality STA/SI/SSTA analyze
 

phutanesv

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Dudes,

Hope this is also a method

1) Planning and specification- likr project planning, test bech spec, verification plan
2)Design coding- Using HDL's
3)Test bench and Test cases creation-functionality Check
4)Verification
5)Synthesis- Cadence SoC enconuter,PTA,Astro any one
6)STA
7)Syntheis netlist verification
8)DFT - BIST in case of Memory design- MBIST.LBIST
9)Boundary Scan-Synopsys tool
10)Floor Planning-Cadnece Soc Encounter
11)partitoning-cadence SoC encounter
12)PnR- Cadence Nanoroute
13)Extraction Of parastic
14)Timing verification
15)Sign-off

Also differnent vendors follow diffrent steps. Cadence follow a way

magma follow another. If all tools are avaliable then i deoends on backend ppl how quick they realse GDSII netlist

Phutnae
 

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