Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Cadence RTL compiler SDF report

Status
Not open for further replies.

kenambo

Full Member level 6
Full Member level 6
Joined
Feb 26, 2012
Messages
393
Helped
52
Reputation
104
Reaction score
48
Trophy points
1,308
Location
India
Visit site
Activity points
3,859
Hi all,

I generated SDF file using write_sdf command in rtl compiler.

While i am analysing sdf file, i came across many terms like ABSOLUTE
TIMINGCHECK IOPATH.

I know the definitions for the above but what makes me confuse is, the values which are given after these paths.

For example,

(IOPATH (POSEDGE CLK) Q :):202) :):166))

what does the values (202 and 166) imply ?

thanks
 

The numbers are delays from clk to q ...which comes in triplets min:Typ:max. in your example you don't have typical and min =0 ..so the only numbers are max delays for the path.

It depends on how you have enable sdf backannotation, what timing corner .libs you are using....max/min/typ.
 
thanks for your help.

I understood now. can you please specify what is sdf back annotation?

i read many pages regarding multi cycle paths.

so multi cycle path depends on propagation delay of a long circuit?

thanks
 

Back annotation as the name implies refers to taking the delays specified in the SDF and applying those delays to the netlist so that delays make themselves apparent during simulation. We call it so because the SDF is obtained after the netlist but the delays from the SDF are again used while working with the netlist.
Your idea about multicycle paths is right.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top