Hi aravind,
Thank you for the reply. The problem is, when I synthesize the top level, it runs with few incr_delay, but timing is not fixed...
When I synthesize module A or B, many rounds of incr_delay in the log, at the end timing is almost fixed, critical path delay is about 400ps.
When I synthesize a top-level module (consists two module A and one copy of module B), the critical path is the same, only a couple of incr_delay operations were run, at the end timing is not fixed well, many instances along the critical path are (p), critical path delay is about 700ps.