Cadence report of pin location

[mamadmn]

Hi,
I created the layout-XL from schematic in Cadence and now I want to find the pin locations and component (transistor's terminals) locations from a report. And then by using these info I plan to route the nets myself.
Would you please let me know how to find such report?

Thanks

 

[Marben Orallo]

Hi,
You can use virtuso SKILL script to find the pin locations
and components locations from your layout .


Regards,
Marbs

 

[erikl]

Would you please let me know how to find such report?

Should be possible with CALIBRE's extract tool, s. here:

#############################################################
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## C A L I B R E S Y S T E M ##
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## C I R C U I T E X T R A C T I O N R E P O R T ##
## ##
#############################################################


REPORT FILE NAME: opamp.lvs.report.ext
LAYOUT NAME: opamp.calibre.gds ('opamp')
CREATION TIME: Fri Jul 2 10:02:10 2004
CURRENT DIRECTORY: /user/sallyw/training/calibrei/rundir
USER NAME: sallyw
CALIBRE VERSION: v2004.1_5.29 Wed Apr 7 23:26:06 PDT 2004



WARNING: Cannot enable LVS PUSH DEVICES because pin location information was requested.

 

[mamadmn]

Hi erikle,
Thank you for your reply.
Actually, I need the x-y coordinates of pins on layout.
Would you please let me know if I should change any switches in the Calibre LVS to report me the pin or device locations?

Regads

 

[erikl]

Sorry, I don't know Calibre well enough. Try and get the info from the Calibre manual.

Here's a skill program to extract pad coordinates. Perhaps you can use it, with appropriate editing:

---

Code  - [expand]
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procedure( PadCoMenu(@optional (phys_Layer nil) (name_Layer nil))
 
glayerframe=hiCreateFrameField(
?name 'glayerframeid
?labelText "Layers definitions"
?enabled t
)
 
gtext1frame=hiCreateFrameField(
?name 'gtext1frameid
?labelText "     This layer must be copied at the top level"
?enabled t
)
gtext2frame=hiCreateFrameField(
?name 'gtext2frameid
?labelText "     ( You can generate it :  pad or pad = pad )"
?enabled t
)
techFile = techGetTechFile(geGetEditCellView())
phys_Layer = hiCreateLayerCyclicField(techFile "Physical Layer of Pads" "" leGetValidLayerList(techFile) car(geGetSelSet())~>lpp)
phys_Layer->hiFieldSym='field1
name_Layer = hiCreateLayerCyclicField(techFile "Layer of Pads Names   " "" leGetValidLayerList(techFile) car(geGetSelSet())~>lpp)
name_Layer->hiFieldSym='field2
 
hiCreateAppForm(
?name 'PadCoForm
?formTitle "Pads Coordinates"
?fields  list(
list(glayerframe 10:0 300:150 20)
list(phys_Layer 18:25 250:39 155)
list(gtext1frame 15:65 290:20 15)
list(gtext2frame 15:80 290:20 16)
list(name_Layer 18:105 250:39 155)
) ; list
?callback "CCSpadCoord()"
) ; hiCreateAppForm
hiDisplayForm(PadCoForm)
) ; procedure
 
procedure( CCSpadCoord( )
 
;prog( (obj objlist1 objlist2 newObjects physLayer nameLayer)
;if(!geGetSelSet() then
;printf(" \n")
;printf("Select something first dunderhead!")
;printf(" \n")
;return(nil)
;)
 
;obj=nil
;objlist1=geSelSet()
;objlist2=nil
 
; declares local variables that will be cleared when the program exits
  let( (cv myPort allpins allpads physLayer nameLayer)
 
physLayer=phys_Layer->value
nameLayer=name_Layer->value
; if fromLayer is only the layer name then
; get the purpose from the selected object itself
if( length(physLayer)==1 then
physLayer=list( physLayer cadr(car(geGetSelSet())~>lpp) )
)
if( length(physLayer)==4 then
physLayer=parseString( cadddr( physLayer ) " ()" )
)
; if fromLayer is only the layer name then
; get the purpose from the selected object itself
if( length(nameLayer)==1 then
nameLayer=list( nameLayer cadr(car(geGetSelSet())~>lpp) )
)
if( length(nameLayer)==4 then
nameLayer=parseString( cadddr( nameLayer ) " ()" )
)
 
cv=geGetWindowCellView()
; opens a file handle to write the output
myPort = outfile("./myPadCoordinates.log")
 
printf("\n---------------------------------------------------------\n\n")
printf("analyzing the cell :  %s   %s \n\n",cv~>libName,cv~>cellName)
printf("Physical layer : %s  %s\n",car(physLayer),cadr(physLayer))
printf("Pad Name layer : %s  %s\n\n",car(nameLayer),cadr(nameLayer))
 
; the following code only identifies metal1 pin
;allpins = setof(x cv~>shapes (x~>purpose=="pin" && x~>layerName=="metal1"))
;if pins of all layers are required, use this instead
allpins = setof(x cv~>shapes (x~>layerName==car(nameLayer) && x~>purpose==cadr(nameLayer)))
; the following code identifies all the pads
allpads = setof(y cv~>shapes y~>layerName==car(physLayer))
 
;foreach( pinshape allpins
;  printf("\npin : %s\t\t%e\t%e\n",pinshape~>theLabel,car(centerBox(pinshape~>bBox)),cadr(centerBox(pinshape~>bBox)))
;)
;foreach( padshape allpads
;  printf("\npad : \t\t%L\t%e\t%e\t%e\t%e\n",centerBox(padshape~>bBox),leftEdge(padshape~>bBox),rightEdge(padshape~>bBox),bottomEdge(padshape~>bBox),topEdge(padshape~>bBox))
;)
 
                     
printf("Pad coordinates will be written to a log file named myPadCoordinates.log\n")
; use fprintf instead of printf when writing to a file
printf("Pad coordinates list created on : %s\n\n" getCurrentTime())
fprintf(myPort "Pad coordinates list created on : %s\n\n" getCurrentTime())
printf("Pad name\t\tCentre Coordinates\n")
fprintf(myPort "Pad name\t\tCentre Coordinates\n")
printf("========\t\t==================\n")
fprintf(myPort "========\t\t==================\n")
; for each pin in the layout, check the corresponding pad below it
padnum = 0
 
foreach( pinshape allpins
  foreach( padshape allpads
    if( 
     ; a pad is associated with a particular pin if it encloses it
     (leftEdge(padshape~>bBox) < car(centerBox(pinshape~>bBox))) &&
     (rightEdge(padshape~>bBox) > car(centerBox(pinshape~>bBox))) &&
     (bottomEdge(padshape~>bBox) < cadr(centerBox(pinshape~>bBox))) &&
     (topEdge(padshape~>bBox) > cadr(centerBox(pinshape~>bBox)))  then
     ;option adds tab spacing to the output
                                                                           
fprintf(myPort " %s\t\t\t%L\n",pinshape~>theLabel,centerBox(padshape~>bBox))
printf(" %s\t\t\t%L\n",pinshape~>theLabel,centerBox(padshape~>bBox))
padnum = padnum +1
))) ; if , foreach , foreach
fprintf(myPort "========\t\t==================\n")
fprintf(myPort "\nNumber of pads : %d \n\n",padnum)
printf("Number of pads : %d \n",padnum)
printf("\n\n---------------------------------------------------------\n")
close(myPort) ; close the file handle
myPort = nil  ; remove it from memory
);end of let
);end of procedure

---

 

[slizak]

Pin locations go in the SVDB directory, unless a command is overriding it. (As hinted at in Erikl's transcript example, you might want to do that if you are pushing devices.) Check that the MASK SVDB command includes "CCI" or "PINLOC"; it should _not_ have "NOPINLOC".

Also, are you sure it is not already in your LVS report? See "Instance Pin Identification" in the Calibre Verification User's Manual. Here's a link to a recent edition on SupportNet:
**broken link removed**

 

[mamadmn]

Thank you for your help
I found the pin locations in the LVS report.
Actually, I need all the location of device terminals listed in the netlist.
Is there any report to find such report from LVS?

Regards

 

[slizak]

Not sure exactly what you are looking for. When you say "device", are you referring to the low-level devices (what Calibre means) such as transistors or something more complex? Also, are you asking where they are in the netlist or for X Y coordinates again?

On the assumption you mean something higher than capacitors, diodes, etc., you are going to either need to check the layout or do some tracing between subcircuit calls. Identify the one that represents your device*, then find the instances (subcircuit calls - begin with an X). The instances will have the $X and $Y for specific device pins, if coordinates were not suppressed. The instances may be several deep, and intermediate coordinates might be relative to a cell rather than the overall design.

* Depending on your setup, the device may not map to a single subcircuit in the generated netlist. To be sure it will be present, you need to explicitly call it out as either an hcell or using an LVS Box statement. (Hcells are used as seeds for matching hierarchy between layout and source; LVS Box is used to indicate areas to not compare.) From the Calibre Verification manual: "Subcircuits are written by the hierarchical SPICE netlister for hcells, LVS Box cells (not when the BLACK or GRAY keywords are used), and cells created by the hierarchical database constructor (ICV_* cells). If the tool is run with the -flatten option, then there is only one subcircuit."

**broken link removed**

 

[mamadmn]

Thank you for your help and I am sorry if my posting was not clear.
Actually, I want to route the circuit myself. So, I already worked with Cadence VCAR (Virtuoso Chip Assembly Router) and I found it can produce the connectivity of transistor terminals (a Network) as follows:
(network
# Network file created by Virtuoso Chip Assembly Router V11.2.41.05 made 2007/01/08 at 12:48:05 (32bit addresses)
(net VDDD (pins |M0-S_2 |M0-S_1 |M3-S_2 |M3-S_1 |M1-S_2 |M1-S_1 |M2-S_2 |M2-S_1 |M2-B |M2-S |M1-B |M1-S |M3-B |M3-S |M0-B |M0-S))
(net VINN (pins |M8-G_7 |M8-G_5 |M8-G_3 |M8-G_6 |M8-G_4 |M8-G_2 |M8-G_1 |M8-G))
(net VINP (pins |M6-G_7 |M6-G_5 |M6-G_3 |M6-G_6 |M6-G_4 |M6-G_2 |M6-G_1 |M6-G))
(net VLATCH1 (pins |M3-G_7 |M3-G_5 |M3-G_3 |M3-G_6 |M3-G_4 |M3-G_2 |M3-G_1 |M1-G_7 |M1-G_5 |M1-G_3 |M1-G_6 |M1-G_4 |M1-G_2 |M1-G_1 |M1-G |M3-G))
(net VLATCH2 (pins |M10-G_5 |M10-G_3 |M10-G_4 |M10-G_2 |M10-G_1 |M11-G_5 |M11-G_3 |M11-G_4 |M11-G_2 |M11-G_1 |M11-G |M10-G))
(net VOUTN (pins |M0-D_1 |M1-D_1 |M2-G_7 |M2-G_5 |M2-G_3 |M2-G_6 |M2-G_4 |M2-G_2 |M2-G_1 |M12-D_1 |M13-G_5 |M13-G_3 |M13-G_4 |M13-G_2 |M13-G_1 |M13-G |M12-D |M2-G |M1-D |M0-D))
(net VOUTP (pins |M0-G_7 |M0-G_5 |M0-G_3 |M0-G_6 |M0-G_4 |M0-G_2 |M0-G_1 |M3-D_1 |M2-D_1 |M12-G_5 |M12-G_3 |M12-G_4 |M12-G_2 |M12-G_1 |M13-D_1 |M13-D |M12-G |M2-D |M3-D |M0-G))
(net VREFN (pins |M7-G_7 |M7-G_5 |M7-G_3 |M7-G_6 |M7-G_4 |M7-G_2 |M7-G_1 |M7-G))
(net VREFP (pins |M9-G_7 |M9-G_5 |M9-G_3 |M9-G_6 |M9-G_4 |M9-G_2 |M9-G_1 |M9-G))
(net VSSS (pins |M10-S_1 |M11-S_1 |M9-B |M8-B |M7-B |M6-B |M13-B |M12-B |M11-B |M11-S |M10-B |M10-S))
(net net30 (pins |M11-D_1 |M7-S_2 |M7-S_1 |M9-S_2 |M9-S_1 |M9-S |M7-S |M11-D))
(net net31 (pins |M12-S_1 |M6-D_1 |M7-D_1 |M7-D |M6-D |M12-S))
(net net050 (pins |M13-S_1 |M8-D_1 |M9-D_1 |M9-D |M8-D |M13-S))
(net net094 (pins |M10-D_1 |M6-S_2 |M6-S_1 |M8-S_2 |M8-S_1 |M8-S |M6-S |M10-D))
)

VCAR can rout the circuit based on the above information. I couldn't find a way to extract the location of these terminal by VCAR.
I need the location of the above terminals in the layout and then I want to route them by my algorithm.
My question is if there is a way for finding such terminal locations?