Mar 12, 2018 #1 R Rajashekar_m Newbie level 1 Joined Feb 27, 2018 Messages 1 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 9 Hi am doing LINT analysis for our design using cadence HAL it generates a warning as halstruct: *W,FFWASR (../../test.v,620|0): Flip-flop 'a47' does not have any asynchronous set or reset. a47 <= out47; We designed the logic using synchronous reset mechanism only. How can i analyze the above warning ? Can i ignore it? regards raj
Hi am doing LINT analysis for our design using cadence HAL it generates a warning as halstruct: *W,FFWASR (../../test.v,620|0): Flip-flop 'a47' does not have any asynchronous set or reset. a47 <= out47; We designed the logic using synchronous reset mechanism only. How can i analyze the above warning ? Can i ignore it? regards raj
Mar 12, 2018 #2 dpaul Advanced Member level 5 Joined Jan 16, 2008 Messages 1,799 Helped 317 Reputation 635 Reaction score 342 Trophy points 1,373 Location Germany Activity points 13,071 We designed the logic using synchronous reset mechanism only. Click to expand... Then the warning msg makes sense. How can i analyze the above warning ? Click to expand... By looking at your RTL code and comparing it with the translated flop after synthesis. Can i ignore it? Click to expand... I don't know your design, so can't comment on it.
We designed the logic using synchronous reset mechanism only. Click to expand... Then the warning msg makes sense. How can i analyze the above warning ? Click to expand... By looking at your RTL code and comparing it with the translated flop after synthesis. Can i ignore it? Click to expand... I don't know your design, so can't comment on it.
Mar 12, 2018 #3 T ThisIsNotSam Advanced Member level 5 Joined Apr 6, 2016 Messages 2,548 Helped 397 Reputation 794 Reaction score 463 Trophy points 1,363 Activity points 14,760 Rajashekar_m said: Hi am doing LINT analysis for our design using cadence HAL it generates a warning as halstruct: *W,FFWASR (../../test.v,620|0): Flip-flop 'a47' does not have any asynchronous set or reset. a47 <= out47; We designed the logic using synchronous reset mechanism only. How can i analyze the above warning ? Can i ignore it? regards raj Click to expand... This is why FFWASR is a warning and not an error. It's benign for this design as you know that was not the intention.
Rajashekar_m said: Hi am doing LINT analysis for our design using cadence HAL it generates a warning as halstruct: *W,FFWASR (../../test.v,620|0): Flip-flop 'a47' does not have any asynchronous set or reset. a47 <= out47; We designed the logic using synchronous reset mechanism only. How can i analyze the above warning ? Can i ignore it? regards raj Click to expand... This is why FFWASR is a warning and not an error. It's benign for this design as you know that was not the intention.