Cadence layout NMOS p substrate connection

[gsbkbharath]

Iam drawing a layout in Cadence for a 2 input nand gate.In the Pull down network i used a p substrate for each of the NMOS. For the lower NMOS i connected the substrate to Ground.But, when i connect the substrate of the upper NMOS to the its source as in the schematic,i get the errors
"p substrate stamp error mult,psubstrate stamp error connect" in DRC. Can't we connect the p substrate of a NMOS to its source directly or we have to use some via?Thanks in advance..

 

[erikl]

The NMOS transistors all share the same p-substrate. So you have to connect the bulk connection of the upper NMOS to the p-substrate, too, not to its source!. The NMOS' bulk is identical to the p-substrate. Just add a P+ contact area next or adjacent to the N+ source, and connect it by via and metal_1 to GND - like the lower NMOS.

 

[gsbkbharath]

Hi erikl. But in NAND for the upper NMOS, the body(p substrate) should be connected to source right?
I feel i am lost here.
I have these doubts.
is the p substrate not the body or bulk of the NMOS?
also nwell not the body or bulk of the PMOS?
Thanks again.

 

[nitishn5]

If you want to connect the substrate connections for both the NMOS transistors to their sources then you would need to isolate them in separate P-Wells and use deep N-Wells for isolation.

 

[erikl]

... in NAND for the upper NMOS, the body(p substrate) should be connected to source right?

No. See above!

is the p substrate not the body or bulk of the NMOS?

Sure it is!

also nwell ... the body or bulk of the PMOS?

Yes, it is!