riteshj
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Hi All,
I'm doing a project in Cadence encounter where I need an even number of inverters in a chain, basically to form a delay line. However, when I look at the generated schematic, I can see that tool has removed all inverters and simply connected I/O net. I think this is due to internal optimization. Can someone help me to get around this problem? I am a noob and I dont know much about TCl scripting. I am giving this chain of inverters as a netlist in my verilog file.
I'm doing a project in Cadence encounter where I need an even number of inverters in a chain, basically to form a delay line. However, when I look at the generated schematic, I can see that tool has removed all inverters and simply connected I/O net. I think this is due to internal optimization. Can someone help me to get around this problem? I am a noob and I dont know much about TCl scripting. I am giving this chain of inverters as a netlist in my verilog file.
