conmourtz
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Hello i am using synopsys design compiler and cadence encounter to create a chip. i have a question. i am at import netlist phase. which commands i need to use at synopsys design compiler so the netlist that will be produced be the right one for encounter? here are the commands that i use:
analyze -format verilog $my_verilog_files
elaborate $my_toplevel
create_clock -period 10 -name CLK [get_ports clk]
# Check for warnings/errors
check_design
set_input_delay 0 -clock CLK [all_inputs]
set_output_delay 0 -clock CLK [all_outputs]
set_max_delay 3 -from [all_inputs] -to [all_outputs]
set_max_area 0
set_max_dynamic_power 0
set_false_path -from [get_ports reset]
uniquify
compile_ultra
write -hierarchy -format verilog -output toplevel_post_synth.v
write_sdc constraints.sdc
is this right or i need to change/ import something else?
ty
analyze -format verilog $my_verilog_files
elaborate $my_toplevel
create_clock -period 10 -name CLK [get_ports clk]
# Check for warnings/errors
check_design
set_input_delay 0 -clock CLK [all_inputs]
set_output_delay 0 -clock CLK [all_outputs]
set_max_delay 3 -from [all_inputs] -to [all_outputs]
set_max_area 0
set_max_dynamic_power 0
set_false_path -from [get_ports reset]
uniquify
compile_ultra
write -hierarchy -format verilog -output toplevel_post_synth.v
write_sdc constraints.sdc
is this right or i need to change/ import something else?
ty