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Hi all,
I am designing an inverter on cadence, now I have an error I can not solve, please help me...
(Gates not over TG) NOT covered by GRLOGIC) OR ((Gates not over TG) under QT MIM capacitor), must have a RX tiedown by M1 metal
Thank you!
Leon
I am designing an inverter on cadence, now I have an error I can not solve, please help me...
(Gates not over TG) NOT covered by GRLOGIC) OR ((Gates not over TG) under QT MIM capacitor), must have a RX tiedown by M1 metal
Thank you!
Leon