Cadence Assura Layout circuit extraction

[pbuccella]

Hi All,

I have a IC layout in a given process technology and I would like to extract the circuit schematics netlist with cadence Assura extraction tool.
I have the process technology design-kit installed and working.
Is it possible to extract the netlist even if the LVS is not clean?

Thanks,

Pietro

 

[dick_freebird]

Extract comes before LVS, it's how LVS gets layout data
(connectivity) to chew on.

Now, getting to the analog_extracted view with parasitics,
that probably needs clean LVS to get the pcapacitors on
the right nets and so on.

 

[pbuccella]

Thank you for your answer.
Actually I need the extraction of the layout netlist without the parasitics. I am writing the extract.rul file and the only way to debug is running repeatedly LVS and the extraction tool QRC.
Thats why I asked if there is a faster way to extract the layout netlist without doing the full LVS.

Thanks,
Pietro

 

[erikl]

I have the process technology design-kit installed and working.

It should include an extract.rul file. And - as dick_freebird mentioned - you don't need to run an LVS after extraction. The extraction provides the extracted netlist.