cadence and synopsis

[jincyjohnson]

whether i can do testing of ISCAS benchmark circuit using scan technique and test patterns. also want to estimate power ,area and fault coverage.actually it is done using synopsis tool.in cadence whether i have to write code in verilog or Vhdl.plzz replyy

 

[rca]

perhap your idea is clear in your mind, but when I read you, I don't where you are in the flow, and what you want to obtain.
for info synopsis does not exist but synopsys.
Synopsys & Cadence tools read verilog or vhdl.