[SOLVED] Cadence analogLib port DC voltage

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The_Dutchman

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Hello all,

I've found a rather strange behaviour in Cadence Virtuoso which I cannot explain instantly.
I use a port from the analogLib library to set a DC voltage. I then sweep this DC voltage from 0 to 0.9V but the output of the port is plotted and seems to be 0-1.8V.
Does somebody has an explanation for this?

Thanks!

 

Such a port by standard has an ohmic generation resistance of 50Ω - and usually expects a load resistance of the same value. So it could be possible, that the original voltage of the source is doubled in order to get the expected value at the load resistance. With a 10kΩ load resistor you measure about double this value, of course. Try with a 50Ω load resistor!

With the analogLib vsource this is not the case (generation resistance = 0).
 
It does assume 50 Ohm load matching, thanks!
 

Hi, Please could you help me with analoglib port problem:

If I find that the input frequency is at all provided from port. What could be the problem?
I'm defining correctly all parameters: VpK - 8m, DC voltage - 800m, Frequency - 1M Hz, resistance 50 Ohm.
I've seen this problem recently. I cannot understand.
For workaround I'm using Vsin. but I need port for HB analysis.
 

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