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c_ver failed generated Verilog file

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bhliuliu

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Dear all,
I am using Synplify Premier H-2013.03-1 as synthesis tool. At the last step Map & Optimizations, it reported me that " @E:MF320 ： | c_ver failed generated Verilog file ", but i do not know how to solve it., pls take me a support, thank you.
 

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