Bus Functional Model in verification methodology

[skynet]

Bus Functional Model

Hi All,

Can anyone here tell me or give me information about Bus Functional Model in verification methodology.

Thanks!

rgds,
Skynet

 

[vomit]

A bus functional model of a processor is a model that just emulates the pins to the outside, not the actual instructions themselves.

In general, a bus functional model will act on its I/O bus as a real model, without doing any of the internal functionality of the chip.

 

[euphonic]

A BFM simply models the bus interface of some unit, it does not contain the RTL or gate level specifics of the unit’s internal workings. The purpose of a BFM is to gain simulation speed, ease of use, and ease of creation.

 

[alledauser]

A bus functional model usually consists of a limited functionality required to test your design. They can mimic bus cycles, interrupt cycles, even complex sequences depending on your test requirements. Since you won't synthesize it, you only use behavioural modeling. Even C language can be used by using PLI. They are only instantiated in test benches. Attached is a text I found on internet on the subject.
regards

 

[joe2moon]

Example of PLI1.0 + Request (.dll)

Some PLI application(s) here:
h**p://www.angelfire.c0m/ca/verilog/examples_pli.html
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PLI1.0 example: 8051 BFM(Bus Functional Model)
Author: Sayed Sohail from Ment0r Graphics
h**p://www.angelfire.c0m/ca/verilog/bfm8051.html
-----------------------------------------------------------------

BTW, is there anyone willing to make the .dll for me ?
Since I do not have the Visual C environment.
-----------------------------------------------------------------

Compilation by Visual C:
> cl -c -I<install_dir>\modeltech\include uc8051.c
> link -dll uc8051.obj <install_dir>\modeltech\win32\mtipli.lib

 

[shiv_emf]

Bus Functional Model

small correction in above link

https://www.angelfire.com/ca/verilog/bfm8051.html

 

[mssajwan]

Bus Functional Model

Hi,
BFM's are transactors with transaction interface on one side and physical level interface on other side.

or simply they are transactors which take some information from one level ,do some processing on it and send it to other level(which should be the pin level interface).

hope this explaination is fine.

thanks
Manmohan