Burn-in Board Design Guidelines For Boards for AEHR Oven

[ling4ever]

Hi,

Can anyone help me on the design guidelines for burn-in boards to be used for AEHR ATS12000 and AEHR Max3 oven? These burn-in boards will be subject to 1000 +/- 72 hours of burn in under constant temperature ranging from +125C to +150C depending on the requirement.

Thank you.

 

[MIL883]

There are plenty of factors involved in this design. First question is are you Burning in the same part or many different parts. If many different parts you will have to make the board "universal" with slots for PCB cards that will have the BURN IN circuitry for the parts you are biasing. There are different Condition requirements, some static using only DC but some are dynamic using the clocks from the connectors inside the AEHR ATS-12000 Chamber. 1000 hours doesnt sound like mil spec, The 2 I am familiar are 496 Hours and 120 Hours with Also you have to consider the current as some parts pull more current than others and a fully loaded Burn in Board with 80 parts may pull up to 12 amps. You have to get more specific in your question - "guidelines" as far as what ? MAterial of PCB, Configuration of Board for maximum parts, trace size ? My Chamber has 2 DC supplies (500 amps) and 1 negative supply (200 amps). We use a "Signal Route Card" on the front end of the Burn In Board to route the signals from the Chamber to where we want them to go- PS1 PS2 plus many clock and address signals. I look forward to your response.

**broken link removed**

 

[ling4ever]

The burn-in boards I design mostly suits a single kind of "device under test" per board and in some cases a single board can be used for a few kinds of devices as long as they belong to the same family. What PCB material do you use for AEHR burn-in boards? Is it FR-408?.. For clock signals, at what frequency do you start using a controlled impedance trace?

 

[MIL883]

G11/FR5-MIL-I-24768/28 -NEMA FR5, but any FR-4 with a rating 20C above your operating temp should be fine. The chamber can clock /address output up tp 2Mhz, at those higher frequencies it depends on the amount of devices in on the board you are clocking. What do you mean "controlled impedance trace"? Basically the larger/ thicker the trace the better off you are on all aspects of criteria, current, impedance, skin effect..... Your launguage and mine seem to differ quite a bit. Did you mean trace thickness? If you have multiple devices on the board (more than 40) sometimes the clock signals degrade and get "loaded down". The load down effect is from the clock signal into multiple low input impedances devices in parrallell. For this problem I have beefed up the mosfet drivers on the clock/driver boards in the rear of chamber to give a much larger current drive to the devices. Are you doing MIL SPEC testing or just Burning in parts as a normal protocol procedure for cell phone devices or something in the commercial market? Its hard to answer questions from a couple general statements. What device are you burning in, I may have an old board I don't use anymore that will work for you. What kind of package, DIP, FLAT PACK, QUAD, LLC, SPIDER ???

 

[ling4ever]

What I mean about control impedance trace are specific trace with the same impedance being kept all through out the board, let say 50-ohm. I am used with automated test equipment (ATE) boards that implements control impedance at nets carrying signals usually above 200MHz. I am starting with burn-in boards and was quite surprise to know that at 20MHz clock they implement this. The burn-in schematic is created by a different group. What I know is that they're using AEHR 12000 oven. Devices being test per board are DAC, ADC, MEMs, etc which are generally automotive grade. Packages are usually DIP, SOIC, FLAT PACK, etc mostly plastic packages. Chamber temp 125C to 150C. It is also a practice to achieve maximum socket density per board so generally the number of sockets ranges from 80 to 160. I admit that there is lack of specs on our burn-in board design for AEHR 12000. I would be glad if you could suggest specifications sheets/documentation of burn-in board design for me to read. Thank you.

 

[MIL883]

Quickly from memory - (I hope this clears things up for you ) BIB design stimulus signals and power/ground levels produced by the system are presented to the burn-in board via dedicated 50 Ohm pins and traces of the BIB edge connector . These signals and power levels must be delivered to the correct socket pins on the BIB to satisfy the pin-out requirement of the devices under test . For this reason, and because signal/power trace routing may differ from DUT type to DUT type, the BIB must incorporate means for programming (scrambling) the signal/power connections for the DUT in question .When specifying a BIB, certain aspects should be considered. Among these are the capabilities of the clock drivers which are capable of an Voltage Out High (VOH) level of +3 .0 volts minimum at 15mA, and a Voltage Out Low (VOL) level of +0 .4 volts maximum at 500mA . The cycle time, address mux, and clock edge circuitry operates in a similar manner to circuitry described above . Oscillators provides a 20MHz clock (50 nanosecond period) to the strobe generators, and to the clock counter . The clock counter divides 20MHz down, and presents eight address lines (A-J) also C1 the cycle time comparator, and to the address mux and clock edge comparators. A comparator composed of exclusive-OR gates accepts other inputs from the cycle time register . When the count matches cycle time data from the register, the CT comparator reloads the clock divider with all zeros, and 2) is used on the Pattern Gen for various Address Mux Lines, the cycle time circuit, the address mux positive and negative comparators accept inputs from the clock counter and the corresponding address mux POS/NEG registers . When the ADR MUX POS or ADR MUX NEG comparator finds a match between inputs A-J and D1-D8, latch U72 is set to the recuired high or low (ADR MUX POS) state . The latch output goes to: 1) address strobe generator which produces output STB ADR upon occurrence of address mux POSitive, and 2) address mux logic of the Patt . Gen . Bd. 10-41 . Clock/Address Strobe Generators ; Clock Generators Address Mux Positive Strobe Generator . When the ADR MUX POS pulse occurs, the comparator forces a low to latch U72, setting its output high and enabling counter U85 . The counter which is clocked at 20MHz counts up from the 4 bit number preset by 4 segment switch S5 . (Note that the preset value is greatest with all switches open, and decreases as the switches are closed in binary fashion) . Upon reaching rollover, the carry output: 1) asserts STE ADR to the Patt . Gen . Bd ., and 2) resets latch U72, thereby disabling the counter with the next clock edge . Thus, signal STB ADS is 50ns long. Clock Strobe Generator . Clock strobe generators STE C1/2, STB C3/4, STB C5/6, and STB C7/8 operate in the same manner as the address raux strobe generator described above . The clock sign POS or NEG, from the comparator sets the latch output enabling the counter . Upon reaching the preset count, rollover resets the latch, stopping the counter, and asserting the clock edge signal . Clock strobe POSitive and IEGative signals are ORed" together for transmission to the Pattern Gen as signals STB Cl/2, STB C3/4, STB C5/6, STB C7/8 C,7/8 . PWR Supply and Reset/Shutdown Circuitry The PS1, PS2, and PS3 control latches are loaded with their programmed voltage values from data bus D1-D8 . Each value is in multiples of 100mv expressed as a binary number . The DAC (digital-to-analog converter) associated with each latch converts this digital signal into an analog voltage which is sent to Driver Boards directly to control voltage regulators for PSI, 2, and 3. The +V REF GEN (U62) provides a factory calibrated voltage to all DACs . Each DAC is factory calibrated by potentiometers and should not recquire field adjustment . A jumper allows the output of the PSI DAC to control a single PS2 supply serving all zones (if the system is so configured) . The highest order bits from PS latches (D7, D8) are monitored by the over-voltage detection circuit to ensure that power supply control signals do not exceed safe levels . Should over-voltage be detected, U2 forces shutdown (SD) and a program fault. This action shuts down the Prog . Bd ., Patt . Gen . Bd ., and Driver Dd . Shutdown may also be caused by:1) a power supply control voltage which exceeds its RFH (reference high) set value 2) remote shutdown (RLIT SD), from the DUT RESET button on the control panel . A shutdown condition is cleared by pressing the local (on board) or remote (on control panel) RESET button . RESET also occurs when.: a) stress/non-stress status changes, and b) during power on by device U87. RESET clears all circuits of the Program and Driver Boards .. Vectors. Vector EPROMs produce signals VO-V15 which may be sent to Driver to be sequentially addressed on a one-to-one ratio with input CT, or at a reduced rate derived by dividing CT by any number from 1- to-255, This action allow s memory usage to be minimized here transitions of c y c l e. The fixed/variable multiplexer supplies a binary number to the clock divider-counter to set the divide-by-number to a value between 1--and-255 . The multiplexer in turn selects these eight lines from either the divide-by-N fixed register (N1-N8) or the divide-by-N variable EPROM/latch (Y1-Y8), as determined by the state of bit P29 . Note that lines N1-N8 are static and do not change for a given sector, whereas lines Y1-Y8 may change value for each increment of EPROM address, depending upon programming of U41 . The clock divider-counter divides CT by the required number to produce a clock for the EPROM address counter . The trailing edge of this signal clocks the EPROM latches, ensuring that vector data is stable when latched . Likewise, the stop address comparator uses the trailing edge of the clock to ensure address data is stable when "compared ." The segment of memory used for a given sector is defined h1i the start bits (Xl-X12) and stop bits (TI-T12) respectively . The EPROM address counter loads start bits X1-X12 and commences counting on the next clock pulse. The stop address comparator monitors stop bits Tl-T12 and compares them with those present on the address bus . When the stop address is reached, the comparator asserts load to the EPROM address counter, loading the start address and renewing the cycle. 10-44 . Address Counter The IS-bit address counter produces eighteen address outputs (HOH17) which serve as working signals for data and address circuits of the Patt . Gen . Bd . This counter is clocked by the cycle tine signal CT . Thus the period of all address lines are multiples of CT . The signals H0-H17 are described below. 10-45 . Data Generation and Clock Outputs Serial data out of the data pattern generator (signal DI) may be programmed to produce numerous patterns . Programming is via bits P1-P18 from EPROM U7 on the Program Bd . When set to high, the 4 selcted P-bit enables the associated address line (1 number Power) to serve as a source signal for Dla As an supplying device (DUTs). Data is thus manipulated to produce test patterns quirreedd by Signal JD bufferedry on a Program Board and sent to Drivers as signal A17. (more to follow tomorrow)