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Thanks, i believe that we can add diodes to bypass the FETs for the sake of inrush.....but yes i see your point, thats even more components.also inrush current capability of the fets
….Interestingly, the above video does not mention this particular EMI problem. The video does however, mention the EMI problem mentioned by asdf44…..if you draw the ckt and work out which nodes are jumping up and down at HF w.r.t. neutral and or the output 0v line - you will see the problem.
….at 34:16 of the video, it mentions this problem, and says that it can be mitigated by implementing a special soft-start in the slow FETs every time the supply crosses through zero.So this topology does have a common mode 'problem' when it switches the low speed leg. That flips neutral from PFC_POS to PFC_NEG instantly forcing the entire PFC bus to make a common mode leap.
and again - no reference to the noise made by the prototypes ....!?!?!?
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and 66 kHz switching, just using GaN for the lower Ron ...
Treez that video is very good. What does 'soft start' mean. You can't pwm that node because there is no inductor there. Have a large dead time and let it soft switch? Maybe.
Thanks, i tend to agree, i just think the noise issues will end up being far worse with control ground being taken as the live line just downstream of the mains input EMC filter. I am amazed that a consultancy would be advocating doing it like this.I can't see any way in which that will work well
Thanks, I see what you mean by this now…after running the simulation, which compares Conventional Boost PFC with BTP-PFC, I can see the problem.So this topology does have a common mode 'problem' when it switches the low speed leg. That flips neutral from PFC_POS to PFC_NEG instantly forcing the entire PFC bus to make a common mode leap.
(Maybe that’s even part of the argument for placing control on the AC
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