Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Bresenham and framebuffer

Status
Not open for further replies.

hdhzero

Newbie level 5
Newbie level 5
Joined
Mar 17, 2013
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,382
Hi guys,

I am designing a really simple GPU and Bresenham line algorithm will be supported. Implementing
the algorithm in VHDL is no problem for me, my problems are on how to use the framebuffer.

My board (de2-115) has a SDRAM with 128MB that I really want to use it as framebuffer so I can save
block ram to other things like caches, buffers, etc.

As many of you may know, SDRAM achieves its best performance when we use bursts to read/write it
and to use this feature, we need consecutive addresses at each burst. The problem is that bresenham may
not generate pixels at consecutive positions.

How could I solve this issue? What I need is an efficient way of moving the generated pixels to the SDRAM.

I've thought on working with tiles:
- generate the first pixel and then determine on which tile we are. Set the appropriated registers
- draw the part of line that is contained in the tile
- stop the bresenham algorithm and transfer the tile to the framebuffer
- repeat the process until all the line has been drawed

The problem with this approach is that I waste more time transferring non-generated pixels than generated pixels.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top