BRAM core generator in xilinx

[sougata_vlsi13]

I am not getting how to load the COE file in the section named as load init file in the xilinx core generator.....is it a file in text document or anything else.....please anybody help

 

[barry]

If you look in the xilinx documentation it very clearly explains the format of the coe file. It should be something like this:

memory_initialization_radix=16;
memory_initialization_vector =0000, 0003, 0006, 0009, 000C, 000F, 0012, 0015, 0019, 001C, 001F;

 

[sougata_vlsi13]

If you look in the xilinx documentation it very clearly explains the format of the coe file. It should be something like this:

memory_initialization_radix=16;
memory_initialization_vector =0000, 0003, 0006, 0009, 000C, 000F, 0012, 0015, 0019, 001C, 001F;

Sir I agree with what u have told but i want to know from where should i browse the document....means should i load it in text file and then load it in the INIT file,I am enclosing some portions of my data in the snapshot that was in ISE text editor...please help me in this regard.

 

[rberek]

You only need a COE file if you want the memory to power up with values other than zero. If you do, you need to create a .coe file yourself and then select that file in Coregen in the part where you can specify an initialization file. Your code shows that you are already initializing the memory in RTL (or so it would appear). If that is the case, you don't need a COE file.

r.b.

 

[barry]

I agree with r.b. What are you REALLY trying to do? There is no need to initialize the memory in RTL-that's just wasting resources. When you use Coregen to create your memory, you just point to the COE file you have created.

 

[sougata_vlsi13]

Thanks everybody for your reply....but sir now one error is coming.The error is that in the AES code which i have written it doesn't have any clock,...be more specific i can say that in the sbox module i didn't use clock but the BRAM core generator has clock....so now the problem is that the proper output is not coming,may be due to some delay in clock....please help...what should i do now

 

[Swapnil Pawar]

i think may b due to clk there is 1 clk cycle delay in the code ?

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i think may b due to clk there is 1 clk cycle delay in the code ?:roll:

 

[rberek]

Well, a few things:

a) We have no idea what your design looks like so we have no way of properly commenting on it.
b) When you did your system design , I assume you sat down and figured out your system timing regarding the BRAM and your AES design. Typically, a designer will review the BRAM datasheets and their own design, figure out timing by doing a timing diagram and and only then integrate the two blocks . It would be especially tricky if the AES block was combinatorial but the BRAM was synchronous. BRAMs need clocks and, depending on the mode used, the data may be delayed during a read.
c) Then a designer will typically simulate their design to see if it behaves as expected.

If you haven't done these things yet, then b) and c) are the things you should do now. If you have done them, post your code with specific descriptions of the problems.

r.b.

 

[sougata_vlsi13]

thank u for your reply