maha_66
Newbie level 4
Hello! I am currently working on a matrix multiplication project. After performing the multiplication of the matrices, I am trying to build a module that can write to memory and can be read from by the UART TX module to send to host pc. What I don't understand is how does inferring a BRAM make it function as a FIFO? Do I need a separate module for a fifo buffer unit? The VHDL book I use has a sentence that I am not sure I understand completely: "Infact, the BRAM module of the Artix device can be configured as a FIFO buffer without any extrernal logic."
I have the following code for inferring a Simple(Sync) Dual Port BRAM for the Matrix Result:
I have the following code for inferring a Simple(Sync) Dual Port BRAM for the Matrix Result:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity bram_simpledual is generic( ADDR_WIDTH: integer := 4; DATA_WIDTH: integer := 16 ); Port ( clk : in std_logic; we : in std_logic ; addr_r, addr_w : in std_logic_vector (ADDR_WIDTH - 1 downto 0); din_a : in std_logic_vector (DATA_WIDTH - 1 downto 0); dout : out std_logic_vector (DATA_WIDTH - 1 downto 0) ); end bram_simpledual; architecture beh_arch of bram_simpledual is type ram_type is array (0 to 2** ADDR_WIDTH - 1) of std_logic_vector (DATA_WIDTH - 1 downto 0); signal ram: ram_type; begin process(clk) begin if(clk'event and clk = '1')then if(we = '1')then ram(to_integer(unsigned(addr_w))) <= din_a; end if; dout <= ram(to_integer(unsigned(addr_r))); end if; end process; end beh_arch;
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