pyrosonic
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Hello,
So far I have only designed systems with microcontrollers, I have not used DSP of FPGA's.
I want to design a BPSK demodulator for a 5MHz signal. The data is sent in bursts normally about 15 bytes long, the symbol rate is 1.25MHz.
After amplification I will be sampling the signal with an 80MSPS A/D converter and decoding the data in a FPGA.
I am basing my design on this : https://www.zipcores.com/binary-psk-demodulator.html which uses a square - filter - divide method of BPSK demodulation.
My questions so far are:
1) Can I use FIR peaking filters instead of IIR peaking filters? FIR filter IP seems to be easily available in FPGA design software.
2) How is the 'Frequency divider /2' implemented? It can't be a digital divider as the result is filtered and multiplied with the original modulated signal.
I have seen a method described here : https://en.wikipedia.org/wiki/Frequency_divider but is says this is an analogue method.
Thanks
So far I have only designed systems with microcontrollers, I have not used DSP of FPGA's.
I want to design a BPSK demodulator for a 5MHz signal. The data is sent in bursts normally about 15 bytes long, the symbol rate is 1.25MHz.
After amplification I will be sampling the signal with an 80MSPS A/D converter and decoding the data in a FPGA.
I am basing my design on this : https://www.zipcores.com/binary-psk-demodulator.html which uses a square - filter - divide method of BPSK demodulation.
My questions so far are:
1) Can I use FIR peaking filters instead of IIR peaking filters? FIR filter IP seems to be easily available in FPGA design software.
2) How is the 'Frequency divider /2' implemented? It can't be a digital divider as the result is filtered and multiplied with the original modulated signal.
I have seen a method described here : https://en.wikipedia.org/wiki/Frequency_divider but is says this is an analogue method.
Thanks
