T
treez
Guest
Hello,
In a boost converter power stage, the dominant pole is 1/(pi.R.C)
Where
pi = 3.14159
R = load
C = output capacitor.
Why is it not 1/(2.pi.RC) ?
...."1/(2.pi.R.C)" is the more " usual" expression, is it not?
Let me elaborate the problem here...
Hello,
How are we to do feedback loop compensation of an SMPS if we cannot derive the feedback loop transfer functions from first principles (eg state space analysis)?
I dare say I stand not alone in being unable to do feedback loop analysis of SMPS’s by first principles……. Please allow me to expand……
Some years ago I worked for a multi million dollar, global telecoms company. You will have heard of it, and you may well own some of its products.
-I worked in the SMPS department, and we were working on SMPS’s for base stations. The lead SMPS design engineer was a highly experienced man with a huge number of successful SMPS projects behind him….he was THE lead design engineer for SMPS’s in this huge organisation.
One day I was trolling through the company’s design network and I stumbled across a folder called “Control”.
Inside this folder I found many of the lead design Engineer’s control documents……..i opened one up which concerned a 55V, 2A boost converter with Vin = 40V.
I found a pole/zero type of analysis where he had listed all the poles and zeros and calculated them.
I was staggered to read one section where he was stating that he did not know why the power stage pole of a boost converter was “1/(pi.R.C)”, instead of “1/(2.pi.R.C)”.
[where R=load and C = output capacitor]
…Surely I thought, the lead SMPS design engineer of a huge company would know this?…….but here are the words he had written in this document…….
…it amazed me that the lead SMPS design engineer didn’t understand.
In another control document, this time for an active clamp forward converter, he had written down what he had used for references in doing his SMPS feedback loop calculations…..here it is…..
…again, I was amazed to find that such an expert was using such commonly available literature….the first two being fairly well directed toward the novice.
So, how do we do SMPS feedback loop analysis in a reliable manner when documents which clearly state each topology’s poles and zeros, including any effects of any slope compensation etc, do not seem to exist?
In a boost converter power stage, the dominant pole is 1/(pi.R.C)
Where
pi = 3.14159
R = load
C = output capacitor.
Why is it not 1/(2.pi.RC) ?
...."1/(2.pi.R.C)" is the more " usual" expression, is it not?
Let me elaborate the problem here...
Hello,
How are we to do feedback loop compensation of an SMPS if we cannot derive the feedback loop transfer functions from first principles (eg state space analysis)?
I dare say I stand not alone in being unable to do feedback loop analysis of SMPS’s by first principles……. Please allow me to expand……
Some years ago I worked for a multi million dollar, global telecoms company. You will have heard of it, and you may well own some of its products.
-I worked in the SMPS department, and we were working on SMPS’s for base stations. The lead SMPS design engineer was a highly experienced man with a huge number of successful SMPS projects behind him….he was THE lead design engineer for SMPS’s in this huge organisation.
One day I was trolling through the company’s design network and I stumbled across a folder called “Control”.
Inside this folder I found many of the lead design Engineer’s control documents……..i opened one up which concerned a 55V, 2A boost converter with Vin = 40V.
I found a pole/zero type of analysis where he had listed all the poles and zeros and calculated them.
I was staggered to read one section where he was stating that he did not know why the power stage pole of a boost converter was “1/(pi.R.C)”, instead of “1/(2.pi.R.C)”.
[where R=load and C = output capacitor]
…Surely I thought, the lead SMPS design engineer of a huge company would know this?…….but here are the words he had written in this document…….
The output capacitor forms the dominant pole with the load resistor ). Thus the gain rolls down at -20dB/ decade, with phase lag heading towards 90 degrees. The frequency of this pole is = 1/pi*R*C ( note NOT 2*pi - I don’t really understand where this comes from, but all the literature seems to say this)”
…it amazed me that the lead SMPS design engineer didn’t understand.
In another control document, this time for an active clamp forward converter, he had written down what he had used for references in doing his SMPS feedback loop calculations…..here it is…..
REFS Ridley - Designing with theTL431
Unitrode( Mammano ): Isolating the control loop
Basso page 286
…again, I was amazed to find that such an expert was using such commonly available literature….the first two being fairly well directed toward the novice.
So, how do we do SMPS feedback loop analysis in a reliable manner when documents which clearly state each topology’s poles and zeros, including any effects of any slope compensation etc, do not seem to exist?
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