Block RAMs implementation...?

[syedshan]

Dear all

I am relatively new to FPGA designing and want to ask regarding BRAMs. If I want to utilize the BRAMs from my V6 FPGA what should I do...
I have written the simple code for memory (different rd/wr channels) and can this be implemented as BRAMs by the synthesis tool XST by selecting
BRAM in synthesis properties -> HDL options -> RAM style

or is there any different method to use the dedicated Block RAMS....

Please if possible answer in detail or atleast hint me to solve the problem...

Many thanks in advance

Regards,
Shan

 

[permute]

XST has very specific requirements for inferrring BRAMs. even trivial changes to the pattern will cause XST to fail to infer BRAMs. check the XST synthesis guide for coding styles that should work.

Alternatively, you can look at the "libraries for HDL designs" manual for the virtex-4/5/6. the v6 can use the components for the v4/5/6. The older components had fewer features, which makes them easier to use.

Stay away from unimacros until Xilinx stops using interns to write VHDL/Verilog. In every experience I've had, I've been able to find several basic errors and annoyances. And for all the work, they still are too limited.

Finally, you can use coregen to generate a core. import the xco file into your ISE project, or place the .ngc file in the ise build directory. I find coregen annoying as there isn't a one-size-fits all RAM/FIFO generator.

(if you do infer BRAMs, remember that the simulation will not show write-write or write-read conflicts or address s/h violations)

 

[prakashvenugopal]

Hi,

You can check the language template tool In ISE in which they had given how to write BRAM Example and the distributed RAM. You can also see the difference between BRAM and Distributed RAM in it and how to utilize it.