Block RAM "read" enable

[shaiko]

After looking into various implementations of Altera block RAM, I noticed that non of them have a "READ" enable pin.
Does this mean that all RAM blocks are of a "look ahead" ("first word fall through") type?

 

[TrickyDicky]

Re: Block RAM "read" enable

What have you been reading? the documentation Im reading says the have a read_enable input.

 

[shaiko]

Please look at following examples.
I don't see any "read_enable" or "read_request" input.

http://www.altera.com/support/examples/vhdl/vhd-dual-clock-syncram.html
http://www.altera.com/support/examples/vhdl/vhd-single-clock-syncram.html
http://www.altera.com/support/examples/vhdl/vhd-true-dual-port-ram-sclk.html
http://www.altera.com/support/examples/vhdl/vhd-single-port-ram.html

 

[FvM]

Please look at following examples.

Each of the examples is using only a subset of available RAM functionality.

Apparently you did not yet read the respective Altera device handbook or the RAM Megafunction user manual.

 

[TrickyDicky]

These are just design examples. But there is this interesting quote in the HDL coding style section of the quartus handbook:

In addition to reset signals, other control logic can prevent memory logic from being
inferred as a memory block. For example, you cannot use a clock enable on the read
address registers in Stratix® devices because doing so affects the output latch of the
RAM, and therefore the synthesized result in the device RAM architecture would not
match the HDL description. You can use the address stall feature as a read address
clock enable in Stratix II, Cyclone® II, Arria® GX, and other newer devices to avoid
this limitation. Check the documentation for your device architecture to ensure that
your code matches the hardware available in the device.

If you read the FPGA documentation, the IV family have read enables. But the enable does not connect directly to the register, it has the address stall instead. The readenable is for asynchronous data output.

 

[shaiko]

The readenable is for asynchronous data output.

What do you mean? Please give an example by code...

 

[TrickyDicky]

Re: Block RAM "read" enable

I think its diffcult to give an example by code, as there are no code examples. Some things just have to be directly instantiated. But to my knowledge, it would be something like:

read_data <= ram(addr_reg) when rd_en = '1' else old_data;

- - - Updated - - -

PS. I dont think I have ever used a read_enable directly on an internal ram. Usually you just keep the read_address constant.

 

[shaiko]

TrickyDicky,
Do you agree with the following statement:

A FIFO implemented with a block ram that doesn't have a read enable signal - will always be a "First Word Fall Through FIFO"

 

[TrickyDicky]

Yes, as it wont have an output register.