Block RAM in xilinx Virtex-II pro

[jkbagada]

Hello friends

I am trying to implement Cache emulator on Virtex-II pro(VHDL).
i wish to use the block RAM available to form cache of 1KB, i dont have any idea about how to use Block RAM and i couldnt follow any online material for the same.

can anybody explain this or suggest some reading material, website or something.


Would be a great help
JB

 

[farhada]

You should check the material that comes with Xilinx ISE 9 or older. There you can find many examples on how to implement Block Ram with VIIP.

This App note may help too:
https://www.xilinx.com/support/documentation/application_notes/xapp260.pdf

 

[jkbagada]

Thanks Farhada

i have generated the BRAM 512x32 using CoreGen and its working fine.......but i didnt initialize it.....
i wish to initialize the RAM with some data..........from internet i learned that either i have to write a .COE file or use an Initialization template......i m confused abt to use these....
can you tell me the exact way to do this.

Thanking you
JB

 

[farhada]

Use the CoreGen to create your memory block and there you can choose to create a .COE file this can help you:
**broken link removed**

 

[jkbagada]

i checked that out but its for FIR filter..... .coe for BRAm would be different rit?

while creating BRAM using CoreGen there was an option of attaching .coe file but i skipped that since i didnt have file at that time...

 

[farhada]

do the same thing again and create one, then you can edit the file in excel or matlab

 

[jkbagada]

thanks farhada

i think it is same as the .coe syntax given on Xilinx website..........can i copy paste this in a text file with .coe extention and attach it with the BRAM ?

 

[farhada]

Yes, these are normal text files, you can edit them manually, use Excel or Matlab as I mentioned earlier.